In electronic design, a predesigned semiconductor logic block (also referred to as an intellectual property core, IP core, or IP block) is a reusable unit of logic, cell, or chip layout design. The “IP” term is derived from patent and source code copyright intellectual property rights that often subsist in the design. IP blocks can be used as building blocks within ASIC (application-specific integrated circuit) chip designs or FPGA (field-programmable gate array) logic designs.
The logic in an IP block may be defined in a register transfer language (RTL) or, alternatively, may be offered as generic gate-level netlists. Subsequent to creation, the IP block is often stored in a library of IP blocks that a developer may insert into a circuit description of a circuit under development.
As integrated circuits continue to become increasingly more complex, it is becoming increasingly more important to embed built-in self tests (BISTs) into a circuit which can be used during design and after manufacture to test the circuit and its various sub-circuits and components. A BIST is often designed as an IP block (BIST IP block) and may be inserted into a circuit description as specified by a designer. The positioning of BIST IP blocks within a circuit description may be referred to herein as the BIST architecture.
A developer may construct chip logic designs as separate design modules, each design module containing a portion of the chip logic and may include one or more IP blocks, including BIST IP blocks. These separate design modules may then be integrated into higher level design modules, forming a design hierarchy, until all design modules are represented in the overall chip design.